April 29, 2014, Ethernet Technology Summit, Santa Clara, CA—Gilles Garcia from Xilinx presented a case for a highly flexible infrastructure to meet the requirements for 400G. Ethernet services in the future. The number of system-level unknowns is the biggest driver.
IP traffic is expected to increase by an order of magnitude in the next four or five years. As a result, the data infrastructure must be improved to handle that volume of traffic. As a proof of concept, Xilinx and Huawei created a prototype to determine technology feasibility and to learn about such future systems through building.
There are many challenges in developing a 400GbE line card. In addition to the raw bandwidth, all the functionality has to be built into a line card that is power and thermal limited. The card must handle electrical and optical signals and communicate at line rates with other parts of the system. The overall system will have a capacity of 819Tbps spread across 64 cards, with each card capable of 12.8Tbps forwarding capability.
A validation platform using 16 X 28Gbps serdes in a Vertex-7 FPGA bridges 40/48 channels of 10/12.5Gb input streams and adds other functionality like loop back and other miscellaneous controls. Internally, the FPGAs use 1280 bit-wide busses running at 312MHz. The test platform achieved a full 400Gbps line loop back with packets from 64 to 1518 bites.
Pre-standard system development through the use of FPGAs permits the design and evaluation of systems while simultaneously permitting the design to track the Ethernet standard as it develops. The Ethernet standard for 400G interfaces is not expected to be finalized until the 2016 or 2017 timeframe, but design validation work must commence now to have the ASICs available when the standard is released.
The inclusion of high levels of hardware programmable functionality enhances the ability to configure systems using software defined networks by creating a software defined specification environment. A "softly" defined network would include a software definition of the data plane set of hardware with content awareness & intelligence. The virtual network services, network flexibility, and holistic management are still defined in the software layer, but the hardware characteristics could be modified through software for even greater flexibility.
The software defined data plane enables wire speed, protocol complexity agnostic interfaces that can be flexibly provisioned on a per flow basis. In addition, system updates can be implemented in either hardware or software. All of these characteristics are part of the SDNet environment which includes a number of packet functions as well as management and provisioning functions across 10/40/100G line rates.
Tools and IP blocks are available for all functions within the SDNet environment, and enable greatly reduced and reusable code for all of the network functions. As a result, designs can be more portable while providing high granularity and flexible architectures. These features facilitate exact services provisioning from core to edge.
